A non-volatile memory device disclosed in patent document 1 includes a memory cell array having a plurality of non-volatile memory cells capable of rewriting data electrically disposed in a matrix. In the memory cell array, an initial setting data region is preliminarily provided as a region for writing various initial setting data necessary for initializing an EEPROM. The initial setting data is the information about memory operating condition.
The memory cell array has a plurality of planes. As shown in FIG. 14, in each plane 110, sixteen memory cells MC are connected in series, and one cell unit NCU is composed, and a plurality of cell units NCU commonly disposing word lines WLn (n=0 to 15) are provided, and cell blocks B0, B1, to Bn are composed as minimum units for erasing data. The plurality of cell blocks B0, B1, to Bn is disposed with, a common bit line BL.
In the plane 110, for example, the cell block Bn is determined as an initial setting data region for storing initial setting data. The initial setting data region reads out initial setting data, same as reading of a normal memory cell, by selective driving of a bit line BL and a word line WLn.
As shown in FIG. 15, when the power is turned on, and the power is stabilized, a reading mode of initial setting data is set. As a result, the initial setting data in the initial setting data region is read out, and validity of this initial setting data is verified. If validity is confirmed (PASS), the read initial setting data is transferred, and if validity is not confirmed (FAIL), a judgement signal is outputted, and the read initial setting data is handled as invalid data, and the chip status is fixed in FAIL state.
Patent document 2 is known as other related art. When turning on the power, current is supplied to bit lines not only through a route passing reading load and first transistor, but also through a route passing second transistor, and it is intended to shorten the time until the bit lines are charged to initial potential.
Patent document 1: Japanese Unexamined Patent Application Publication No. 2004-152413 (FIG. 1, FIG. 2, FIG. 7)
Patent document 2: Japanese Unexamined Patent Application Publication No. 11 (1999)-265595